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黃國棟

黃國棟老師照片

黃國棟（Kuo-Tung Huang） 

職　　稱：助理教授

電子郵件：kdhuanga@mail.lhu.edu.tw

研究領域：半導體元件物理、半導體製程技術、半導體元件調變工程、元件電路佈局效應(LDE)、穿隧場效電晶體(TFET)、雷射封裝模組、光二極體

學經歷：國立中山大學 電機工程研究所 博士
        台灣積體電路股份有限公司 主任工程師

 

研究成果：

國際期刊

International Journal

  1. Jyi-Tsong Lin, and Kuo-Dong Huang, “A High Performance Polysilicon Thin-Film Transistor Built on a Trenched Body”, IEEE Trans. Electron Devices, Feb. 2008. (IF:3.1)
  2. Jyi-Tsong Lin, Kuo-Dong Huang, and Shu-Fen Hu, “Non-Classical Polycrystalline Silicon Thin-Film Transistor with Embedded Block-Oxide for Suppressing the Short Channel Effect”, Semicond. Sci. Technol., vol. 23, Feb. 2008, 075007(6pp).
  3. Jyi-Tsong Lin, Kuo-Dong Huang, and Shu-Fen Hu, “The Effect of a Smart Body Tie on the Bottom Gate Thin Film Transistor”, Solid-State Electronics, vol. 52, Feb. 2008, pp.808-812. (IF:1.1)
  4. Jyi-Tsong Lin, and Kuo-Dong Huang, “Non-classical polysilicon thin-film transistor with symmetric trenched body”, Electronics Letters, vol. 43, no. 24, Nov. 2007, pp. 1390-1392. (IF:1.1)
  5. Jyi-Tsong Lin, Kuo-Dong Huang, and Shu-Fen Hu, “The Effect of N-Channel Polysilicon Thin-Film Transistors with Body-Block Spacers”, Solid-State Electronics, vol. 51, Feb. 2007, pp.1056-1061. (IF:1.7)
  6. Jyi-Tsong Lin, Kuo-Dong Huang, Chu-Lun Wu, “An Alleviated Self-heating Poly-Si Thin-Film Transistor Built on Non-continuing Buried Insulator”, Electrochemical and Solid-State Letters, 10 (3), Jan. 2007, pp. H107-H110.
  7. Jyi-Tsong Lin, Kuo-Dong Huang, and Shih-Tsong Lin, “A Kink-Free Bottom Gate Poly-Si Thin-Film Transistor with Smart Body Tie”, ECS Transactions, 2 (26), 2007, pp. 1-7.
  8. Shu-Fen Hu, Kuo-Dong Huang, Yue-Min Wan, Chin-Lung Sung, “Proximity effect of electron beam lithography on single-electron transistors”, Pramana - Journal of Physics, vol. 67, no. 1, 2006, pp. 57-65. (IF:2.8)
  9. Yue-Min Wan, Kuo-Dong Huang, S. F. Hu, C. L. Sung, and Y. C. Chou, “Coulomb blockade oscillations in ultra-thin gate oxide silicon single-electron transistors”, Journal of Applied Physics, vol. 97, no. 11, 2005, pp. 116106. (IF:3.2)
  10. Shu-Fen Hu, Kuo-Dong Huang, Chin-Lung Sung, Yue-Min Wan, “Proximity effect of electron beam lithography for single-electron transistor fabrication”, Applied Physics Letters, vol. 85, no. 17, Oct. 25, 2004, pp. 3893-3895. (IF:4)

國內期刊

Local Journal

  1. Shu-Fen Hu, Kuo-Dong Huang, Chin-Lung Sung, Yue-Min Wan, “點接觸式單電子電晶體之製作與分析”, 奈米通訊, vol. 11, no. 4, pp. 1-5, 2004.

國際會議

International Conference

  1. Kuo-Tung Huang, Ying-Che Suang, Hsin-Lin Wu, Cheng-Han Wang, Qi-Hong Yang," Chip Level Sub-millimeter Refractor Packaging with Edge Emitting Laser," The International Conference on Flexible and Printed Electronics (ICFPE 2024), Aug. 28-30, 2024, Taipei, Taiwan.
  2. Kuo-Tung Huang, Ying-Che Suang, Hsin-Lin Wu, Sean Wu, Cheng-Han Wang, Qi-Hong Yang," Novel Edge Emitting Laser Packaging with Sub-millimeter Silicon Refractor," International Electron Devices & Materials Symposium (IEDMS), Aug. 19-21, 2024, Taichung, Taiwan.
  3. Jyi-Tsong Lin, Wei-Han Lee, Kuo-Tung Huang, Ruei-Kai Yang, Characterization of Junction-less TFET with Drain Schottky Barrier Contact, 12th International Multi-Conference on Engineering and Technology Innovation 2023 (IMETI2023), October 27-31, 2023, Taoyuan, Taiwan.
  4. Kuo-Tung Huang, Sean Wu, Chien-Chih Chiang, Jeou-long Lee, and Ta-Lun Sung," Layout Dependent Effect Impact on MOSFET Performance by STI Stress," International Electron Devices & Materials Symposium (IEDMS), Oct. 27-28, 2022, Nantou, Taiwan.
  1. Jyi-Tsong Lin, Kuo-Dong Huang, "A Novel Polysilicon Thin-Film Transistor with Multi-Trenched Body for Suppressing Off-State Leakage," IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Dec. 20-22, 2007, Tainan, Taiwan.
  2. Jyi-Tsong Lin, Kuo-Dong Huang, "A Non-Classical Polysilicon Thin-Film Transistor with Symmetric Trenched Body," International Electron Devices and Materials Symposia (IEDMS), Nov. 30-1, 2007, Hsinchu, Taiwan.
  3. Jyi-Tsong Lin, Kuo-Dong Huang, Shih-Tsong Lin, Shu-Fen Hu, Chin-Lung Sung, Ya-Chang Chuo and Pei-jiun Yen, “Fabrication of the Bottom Gate Thin Film Transistor with Smart Body Tie”, International Electron Devices and Materials Symposia (IEDMS), Dec. 7-8, 2006, Tainan, Taiwan.
  4. Jyi-Tsong Lin, Kuo-Dong Huang, Shih-Tsong Lin, Chu-Lun Wu, Chin-Lung Sung, Ya-Chang Chuo and Pei-jiun Yen, "Fabrication of Polysilicon Thin-Film Transistor Built on Poly Buffer LOCOS," International Electron Devices and Materials Symposia (IEDMS), Dec. 7-8, 2006, Tainan, Taiwan.
  5. Jyi-Tsong Lin, and Kuo-Dong Huang, “The Fabrication of Block-Oxide Thin-Film Transistor with Superior Subthreshold Characteristics”, International Symposium on Nano Science and Technology (ISNST), Nov. 2006, Tainan, Taiwan.
  6. Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin, and Kuo-Dong Huang, “High Performance Thin-Film Transistor with L-Shaped Block Oxide”, 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), October 23-26, 2006, Shanghai, China.
  7. Yi-Chuen Eng, Jyi-Tsong Lin, Kuo-Dong Huang, Tai-Yi Lee, and Kao-Cheng Lin, “An investigation of the effects of Si thickness-induced variation of the electrical characteristics in FDSOI with block oxide”, 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct 23-26, 2006, Shanghai, China.
  8. Jyi-Tsong Lin, Yi-Chuen Eng, Kuo-Dong Huang, Tai-Yi Lee, and Kao-Cheng Lin, “Ultra-Short-Channel Characteristics of Planar MOSFETs with Block Oxide”, 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), July 3-7, 2006, Meritus Mandarin, Singapore.
  9. Jyi-Tsong Lin, Yi-Chuen Eng, Kuo-Dong Huang, Tai-Yi Lee, and Kao-Cheng Lin, “A Novel FDSOI MOSFET with Block Oxide Enclosed Body”, International Conference on IC Design & Technology, May 24-26, 2006, Padova, Italy.
  10. Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin, and Kuo-Dong Huang, “A Impact of Block Oxide on 50 nm Gate Length Planar MOSFETs”, International Conference on IC Design & Technology, May 24-26, 2006, Padova, Italy.
  11. Jyi-Tsong Lin, Kuo-Dong Huang, Shih-Tsong Lin, “A Novel Bottom Gate Polysilicon Thin-Film Transistor with Smart Body Tie”, in IEEE 25th International Conference on Microelectronics (MILE), May 14-17, 2006, Belgrade, Serbia and Montenegro.
  12. Kuo-Dong Huang, Jyi-Tsong Lin, Shu-Fen Hu and Chin-Lung Sung, “The Fabrication of Single Electron Transistor by Polysilicon Thin Film and Point-Contact”, in IEEE 25th International Conference on Microelectronics (MIEL), May 14-17, 2006, Belgrade, Serbia and Montenegro.
  13. Jyi-Tsong Lin, Kuo-Dong Huang and Shih-Tsong Lin, “A Kink-Free Bottom Gate Poly-Si Thin-Film Transistor with Smart Body Tie,” in 209th Meeting of The Electrochemical Society (ECS), 601, 17, May 7-12, 2006, Denver, Colorado USA.
  14. Yue-Min Wan, Kuo-Dong Huang, Ching-Lung Sung, and Shu-Fen Hu, “Transport properties of ultra thin oxide gated Si SET near room temperature”, Proceedings of 5th IEEE Conference on Nanotechnology, July 11-15, 2005, Nagoya, Japan.

國內會議

Local Conference

  1. Kuo-Tung Huang, Ying-Che Suang, Hsin-Lin Wu, Sean Wu, Cheng-Han Wang, Qi-Hong Yang, ” Micro Refractor on Edge Emitting Laser Package”, The 4rd Symposium on Nano-Device Circuits and Technologies, SNDCT 2024, Aug. 19-21,2024, Taichung, Taiwan.
  2. 黃國棟*, 吳信賢, 翁文彬, 楊麒弘, 王晟翰 ” 金氧半場效電晶體在淺溝渠隔離製程應力變化之元件佈局效應”, WCE 2023 民生電子研討會, Dec. 2023, Taoyuan, Taiwan.
  3. Kuo-Tung Huang, Sean Wu, Chien-Chih Chiang, Jeou-long Lee, Ta-Lun Sung, Jun-Kai Luo, Jia-Chen Luo, Yu-Cheng Huang, Huang-Jun,Wu, ” Impact Evaluation of Layout Dependent Effects on STI Stress Process”, The 3rd Symposium on Nano-Device Circuits and Technologies, SNDCT 2023, May 2023, Hsinchu, Taiwan.
  1. Jyi-Tsong Lin, Kuo-Dong Huang, and Bao-Tang Jheng, “A High Performance Thin-Film Transistor Built on Block-Oxide N-Channel Polycrystalline Silicon”, 2008 Symposium on Nano Device Technology, May 2008, Hsinchu, Taiwan.
  2. Jyi-Tsong Lin, Kuo-Dong Huang, and Bao-Tang Jheng, “Trenched Body Technology for Use to Suppress Leakage Current in a Ploy-TFT”, in 2008 Microelectronics Technology and Applications Conference, May 16, 2008, Kaohsiung, Taiwan.
  3. Jyi-Tsong Lin, Kuo-Dong Huang, and Yu-Chi Kang, “A High Performance Thin-Film Transistor Built on Block-Oxide N-Channel Polycrystalline Silicon”, 2007 Symposium on Nano Device Technology, May 2007, Hsinchu, Taiwan.
  4. Jyi-Tsong Lin, Kuo-Dong Huang, and Chu-Lun Wu, “A Kink-Free Polysilicon Thin-Film Transistor Built on Local Oxidation of Silicon (LOCOS)”, 2006 Symposium on Nano Device Technology, May 2006, Hsinchu, Taiwan.
  5. Jyi Tsong Lin, and Kuo-Dong Huang, “Single Electron Device Operated in Room Temperature”, 2005 Symposium on Nano Device Technology, May 2005, Hsinchu, Taiwan.
  6. Yue-Min Wan, Kuo-Dong Huang, C. L. Sung and S. F. Hu, “Transport Properties of Point-Contact Si SET near Room Temperature”, 中華民國物理學會年會暨研究成果發表會, Feb. 2005, Sun Yat-Sen Univ., Taiwan.
  7. Kuo-Dong Huang, Yue-Min Wan, S. F. Hu and C. L. Sung, “Single Electron Transistor of Silicon Based Point-Contact Tunnel Junction”, 2004 Symposium on Nano Device Technology, May 2004, Hsinchu, Taiwan.
  8. Kuo-Dong Huang, Yue-Min Wan, S. F. Hu and C. L. Sung, “Single Electron Transistor of Silicon Based Point-Contact Tunnel Junction”, 2004 Symposium on Nano Device Technology, May 2004, Hsinchu, Taiwan.

專利

Patent

  1. Kuo-Tung Huang, et al., “SEMICONDUCTOR PHOTO-DIODE RECEIVER WITH THEIR LASER PACKAGING STRUCTUREe”, patent for republic of china (Applying), 2024 「半導體光學接收器及具有半導體光學接收器的雷射封裝結構」中華民國發明專利 (申請號 113108316 號)。申請中
  2. Kuo-Tung Huang, et al., “Novel Semiconductor Device with Layout Dependence Effect and Method for Forming the Same”, patent for republic of china (Accept), 2022 「新型電路佈局效應之元件製作方法」中華民國發明專利 (申請號 112102336 號)。通過
  3. Kuo-Tung Huang, et al., “Semiconductor Device with Charge Effect Reduction by Plasma Damage and Method for Forming the Same”, patent for republic of china I804379, 1 June. 2023. 「降低半導體元件電漿靜電效應之製作方法」中華民國發明專利 發明第：I804379。
  4. Jyi-Tsong Lin, Kuo-Dong Huang, and Shu-Fen Hu, “Single Electron Transistor and Method for Manufacturing the Same”, patent for republic of china, I 248663, 1 Feb., 2006.
  5. Jyi-Tsong Lin, Kuo-Dong Huang, and Yi-Chuen Eng, “Transistor Device with p-gate and Method for Manufacturing the Same”, patent for republic of china, I 251934, 1 March. 2006.
  6. Jyi-Tsong Lin, Kuo-Dong Huang, and Kao-Cheng Lin, “Trench SOI-DRAM Cell and Method for Manufacturing the Same”, patent for republic of china, I 349996, 1 Oct. 2011.
  7. Jyi-Tsong Lin, Kuo-Dong Huang, and Ho-Ting Chen, “SOI Device with Pseudo Gate-all-around and the Method for Making the Same”, patent for republic of china, I 355691, 1 Jan. 2012.

主持或參與之研究計畫

產學

  1. 企業產學合作計畫，計畫總經費37.7萬，合作廠商: 連盟興業股份有限公司，計畫內容: 半導體低碳化製程之開發，計畫期間: 113年5月至114年4月。
  2. 龍華科技大學企業實務產學合作，計畫總經費50萬，合作廠商: 有光工業股份有限公司，計畫內容: 奈米金屬合金在局部圖形熱應力效應下之特性，計畫期間: 113年2月至113年11月。
  3. 112年度教育部補助技專校院辦理產業學院計畫，計畫總經費21萬，計畫內容: 多層印刷電路板壓合技術優化精進師生實務職能方案，計畫期間: 112年8月至113年7月。
  4. 企業產學合作計畫，計畫總經費35萬，合作廠商: 點量企業股份有限公司，計畫內容: 次毫米轉向鏡之開發，計畫期間: 112年10月至113年3月。
  5. 經濟部工業局產業低碳化輔導計畫，計畫總經費100萬，合作廠商: 南岩半導體股份有限公司、連盟興業股份有限公司，計畫內容: 112年產業低碳與智慧化輔導計畫，計畫期間: 112年7月至112年12月。
  6. 龍華科技大學企業實務產學合作，計畫總經費30萬，合作廠商: 有光工業股份有限公司，計畫內容: 半導體材料具有局部圖形應力效應之研究，計畫期間: 112年2月至112年11月。
  7. 龍華科技大學產學合作計畫，計畫總經費8萬，合作廠商: 瑋展營造，計畫內容: 工程類手冊與教育訓練，計畫期間: 111年12月至112年5月。

國科會

  1. 大專生專題研究計畫，指導教授，計畫編號: 113-2813-C-262-014-E，計畫總經費137.3萬，計畫內容: 多層印刷電路板關鍵壓合技術優化，計畫期間: 2024/07/01 ~ 2025/02/28。
  2. 專題研究計畫(一般研究計畫)，共同計畫主持人，計畫編號: 113-2221-E-110-049 -，計畫總經費137.3萬，計畫內容: 高效能超低功耗感應穿隧場效應電晶體(iTFET):探討與研發，計畫期間: 2024/08/01 ~ 2025/07/31。
  3. 專題研究計畫(一般研究計畫)，共同計畫主持人，計畫編號: 112-2221-E-110 -069 -，計畫總經費83.3萬，計畫內容: 終極場效應電晶體-理想開關的探討和研製，計畫期間: 2023/08/01 ~ 2024/07/31。

證照

  1. 經濟部iPAS 電路板製程工程師初級證照。
  2. GLAD AIL人工智慧國際認證證照。
  3. PVQC電子電機類專家級證書和通過監評人員評鑑認證。
  4. 智泰科技VisLab AI圖像辨識3星級檢定通過。
  5. 貝爾國際驗證 永續報告書管理師 Sustainability Report Management Professional。
  6. 勞動部勞動力發展署桃竹苗分署、工業技術研究院產業學院 綠領人才培訓證書。
  7. Microsoft Azure AI Fundamentals (AI-900)認證。
  8. 英商勞氏(LRQA) 組織溫室氣體盤查主導查證員(ISO14064-1:2018)

競賽

  1. 2024 桃園青創力學生創業競賽，銅牌獎
  2. 2023年民生電子國際研討會最佳論文競賽，佳作。
  3. 2023第十四屆IIIC國際創新發明競賽，Scanning Beam Method to Detect Fiber Defects，第一名。
  4. 2023第十四屆IIIC國際創新發明競賽，Enhance the Corrosion Resistance and Adhesion Properties of Electroless Tin on Printed Circuit Boards，第二名。
  5. 2023第十四屆IIIC國際創新發明競賽，Using Recycled Metal to Create Ceramic-Like Surface Properties，第二名。
  6. 2023第10屆高雄國際發明暨設計展，PREPARATION OF SUPERHYDROPHOBIC SILICA-BASED FILMS，第二名。
  7. 2022第十三屆IIIC國際創新發明競賽，Electroless copper on LED ceramic substrate surface with non-formaldehyde reductant，第一名。
  8. 2022第十三屆IIIC國際創新發明競賽，Ultrasonic-assisted enhancement of zinc content in magnesium alloy micro-arc oxidation coating，第一名。
  9. 2022第十三屆IIIC國際創新發明競賽，Adding particles to the electrolyte improves the wear and lubricity of the aluminum alloy surface，第二名。
  1. 第二屆 全國AI圖像辨識應用競賽_大專院校組，佳作。
  2. 第二屆 全國AI圖像辨識應用競賽_高中職組，第三名。
  3. 2022第十三屆全國電動載具創意設計與製作競賽，36V電瓶驅動馬達靜態比賽，第二名。
  4. 2022第十三屆全國電動載具創意設計與製作競賽，36V電瓶驅動馬達36V動態比賽，佳作。
  5. 2022年第四屆綠點子國際發明暨設計競賽，感應加熱爐，銅牌。
  6. 2022年第二十屆全國電化學車(Chem-E-Car)競賽_高職組，第四名。
  7. 2022年第二十屆全國電化學車(Chem-E-Car)競賽_大專組，團體合作獎。